This application claims the priority benefit of Taiwan application serial no. 90104468, filed Feb. 27, 2001.
1. Field of Invention
The present invention relates to a method of manufacturing multilevel interconnects. More particularly, the present invention relates to a method of manufacturing a cap layer or etching stop layer with improved surface wetting ability.
2. Description of Related Art
As dimensions of metal-oxide-semiconductor (MOS) transistor are shrunk to increase the level of integration of integrated circuits, more interconnects are required to connect the MOS transistors. An available area on a chip surface is not sufficient to accommodate all the necessary interconnects. This insufficiency is cured by employing an integrated circuit having two or more metallic layers, in other words, multilevel interconnects.
For advanced technology, it becomes a trend in the fabrication of semiconductor devices to use copper as the material for forming interconnects. This is because copper has a low resistivity and a high resistance of electromigration. Moreover, a copper layer can easily form over a substrate by electroplating or chemical vapor deposition. Hence, copper is frequently adopted in the fabrication of multilevel interconnects especially for deep sub-micron devices.
One conventional process of forming the multilevel interconnects is known as a dual damascene process. First, a dielectric layer is formed over a substrate. The dielectric layer is next etched, according to the desired conductive wire pattern and position of the via hole, to form a trench and a via hole. In other words, the lower portion of the dielectric layer is etched to form a vertical via hole that exposes a device region or a conductive wire in the substrate. This is followed by etching the upper portion of the dielectric layer to form a horizontal trench. Metallic material is deposited over the substrate to form a metallic layer that completely fills the trench and the vertical via hole, thereby forming a conductive wire and a via at the same time. After that, the upper surface is planarized by chemical-mechanical polishing before forming a cap layer on the substrate. Finally, another dual damascene structure is similarly formed in the horizontal trench and the vertical via opening over the substrate to complete a dual damascene process.
Alternatively, the dual damascene structure above can be formed by first forming a first dielectric layer, followed by forming a middle etch stop layer on the first dielectric layer. A second dielectric layer is then formed on the middle etch stop layer. The second dielectric layer is etched until the middle etch stop layer is exposed to form a horizontal trench. Finally, the first dielectric layer is etched until the cap layer is exposed to form a vertical via opening. This completes fabrication of the dual damascene structure.
When CMOS devices continue to shrink especially down to 0.18 xcexcm generation and beyond, wiring delay due to multilevel interconnect becomes a dominant factor. To overcome the delay caused by capacitance effect when devices continue to shrink, a low dielectric constant material such as spin-on-polymer (SOP) is often used to form a low dielectric constant layer. However, such low dielectric constant materials are usually high molecular weight organic compound. On the other hand, material forming the cap layer is usually an inorganic dielectric compound such as silicon nitride or silicon carbide. In general, an organic low dielectric constant material has poor adhesion with an inorganic dielectric material. In other words, the poor coating/adhesion could be closely resulted from the poor wetting ability of an interface between the upper spin coating material and the under layer.
In addition, the cap layer is mainly used to prevent the diffusion of copper atoms. Most cap layers are made from silicon nitride or silicon carbide. Between silicon nitride or silicon carbide, the latter has a dielectric constant K (about 4-5) lower than the former, and silicon carbide has a better resistance to prevent the outward copper diffusion. Hence, silicon carbide is a better choice for acting as a barrier layer between a metallic layer and a dielectric layer. Intrinsically, the silicon carbide layer exhibits hydrophobic behavior. In terms of wetting ability for aqueous solution, silicon carbide would not exhibit a better coating/wetting ability with the upper layer, i.e. adhesion promoter, and with the following SOP low K material.
Accordingly, the first objective of the present invention is to provide a method of manufacturing multilevel interconnects having an enhanced wetting ability on a surface of the under layer.
The second objective of the invention is to provide a method of manufacturing multilevel interconnects capable of preventing the electromigration of copper.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing multilevel interconnects. A dual damascene interconnect structure is formed with a cap layer is first formed over the interconnect structure. The cap layer is treated with a nitrogen-containing plasma treatment to modify the hydrophobic surface of silicon carbide into a hydrophilic surface. Then, an adhesion promoter layer is coated over the cap layer. After baking, solvent within the adhesion promoter layer is driven off. Thereafter, a low dielectric constant material is formed over the adhesion promoter layer followed by a bake and cure process for solvent removal and polymerization (cross-linking). A dual damascene opening is formed by patterning and etching the second dielectric layer. A barrier layer is formed over the exposed surface of the opening. A conductive material is deposited into the opening to form a multilevel interconnect.
The invention also provides a similar method of manufacturing multilevel interconnects. A first dielectric layer, a dual damascene interconnect structure, a cap layer, and a second dielectric layer are formed over a substrate. A middle etch stop layer is formed on the second dielectric layer, while the middle etch stop layer is treated with gaseous nitrogen to convert its hydrophobic surface into a hydrophilic surface. An adhesion promoter layer is formed over the middle etch stop layer, while solvent within the adhesion promoter layer is removed by baking. Thereafter, a third dielectric layer is formed over the adhesion promoter layer followed by a curing step to polymerize the third dielectric layer or to form a 3-dimensional crosslink in the third dielectric layer. A dual damascene opening is formed in the third dielectric layer. A barrier layer is formed over the exposed surface of the opening. A conductive material is deposited into the opening to form a multilevel interconnect.
According to this embodiment, one major aspect of this invention is the nitrogen gas treatment to the surface of the cap layer or the middle etch stop layer so that its surface changes from hydrophobic to hydrophilic. Hence, the wetting ability of the cap layer or the middle etch stop layer is increased and coating with the adhesion promoter and low dielectric constant material is much improved.
In addition, since both the cap layer and the dielectric layer are formed using lower dielectric constant material compared to the conventional dielectric materials, a semiconductor device having dielectric layers with low effective dielectric constant is achieved.
Furthermore, the cap layer or the middle etch stop layer above the interconnect structure can serve not only as a barrier that prevents the electromigration of copper atoms into the second dielectric layer, but also can serve as an etching stop layer for controlling etching depth. Therefore, over-etching into the under dielectric layer is avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.